Embodiments of the present embodiments relate to a semiconductor controlled rectifier (SCR) for electrostatic discharge (ESD) protection of lateral double-diffused metal oxide semiconductor (LDMOS) devices having a programmable switching voltage.
Referring to FIG. 1A, there is a current-voltage diagram of a semiconductor controlled rectifier (SCR) of the prior art. FIG. 1B is a simplified diagram of the SCR together with a double diffused metal oxide semiconductor (DMOS) transistor 114 as previously disclosed by Efland et al. (U.S. Pat. No. 6,137,140). The diagram of FIG. 1B illustrates the PNPN impurity layers and intervening junctions J1-J3 of the SCR. In particular, regions 120, 122, and 124 form a PNP transistor of the SCR. Regions 122, 124, and 126 form a NPN transistor of the SCR. Resistors 110 and 112 are shunt resistors that prevent forward bias voltages for the PNP and NPN transistors, respectively, during normal circuit operation. Here and in the following discussion it should be understood that a semiconductor controlled rectifier may also be called a silicon controlled rectifier or a thyristor as described by S. M. Sze, “Semiconductor Devices Physics and Technology” 148-156 (John Wiley & Sons 1985). In general, a silicon controlled rectifier is a special case of a semiconductor controlled rectifier that is specifically formed on a silicon substrate. The current-voltage diagram (FIG. 1A) shows a reverse blocking region 100 where junctions J1 and J3 are reverse biased, but junction J2 is forward biased. By way of contrast, junctions J1 and J3 are forward biased, but junction J2 is reverse biased in the forward blocking region 102. At switching voltage Vsw 104, the SCR switches to a minimum holding voltage (Vh) and holding current (Ih) region 106. In this mode all three junctions J1-J3 are forward biased and the minimum holding voltage across the SCR may be as low as a single diode drop or approximately 0.7V. In holding region 106, therefore, the SCR functions as a near ideal switch with very little power dissipation during electrostatic discharge (ESD) stress due to the low holding voltage and holding current.
SCRs have been used for primary protection against ESD for several years. Protection circuit design with DMOS technology, however, presents special challenges due to the relatively high operating voltage and current. For example, DMOS devices may operate in the range of 20V to 100V for various applications. These operating conditions preclude most techniques for adjusting SCR switching voltage and holding voltage as disclosed in the prior art. The switching voltage of the SCR of FIG. 1B is typically determined by the avalanche threshold of p-n junction J2. Junction J2, therefore, is typically designed as a linear junction to withstand the relatively high operating voltage required by DMOS applications. This and other features of DMOS technology present several problems that are resolved by embodiments of the present invention as will become apparent in the following discussion.